Hyperion Entertainment Message Boards

Calgor,

Yes I used "ShowConfig >file Debug" for the output. The numbers were about the same in between the 2 OS's; I did use the "black list" on the bustest in OS 4.1.

To me (qualified as an end-user) the numbers mean CSPPC RAM is about 3 to 4 times faster than "bus" ram; and even with the video ram's low latentcy (refresh rate) the Radeon ram is in the same "ball park" as the Zorro 3 ZorRam. I can, subjectively, tell the difference in ram paged to the ZorRam vs. that paged to the UW Hard drive.

Overall the paging process is smooth and not all that noticeable unless I am looking for it. This, in itself is a fine example of virtual memory management on hardware designed 20+ years ago. Thank you Hyperion Team Amiga!

Dan

Yes, it is pretty good isn't it? Now if only we could replace the CVPPC with a memory card in that slot with 2GB of RAM and update the CSPPC firmware to add 768MB of that between $10000000 and $40000000 (what that space was designed for in OS3.1), and the rest as paged (or elsewhere in memory map if possible) up to the 2GB OS limit, I imagine the CSPPC with OS4.1 would fly! CyberZorRAM anyone? =)

That is actually a brilliant idea! It would have to be associated with a firmware revision, but memory expansion seems to be rather straight forward in the Amiga.

What are your thoughts on the UltimatePPC?

danbeaver wrote: I have those Bus numbers per Calgor's recommendations from my A4000T, CS-ppc with 128MB 60ns RAM, + 16MB motherboard RAM + Radeon 256MB RAM on the Mediator. At the end are the ROM speed and the bus test under OS 4.1 (to be complete).

Just one curiosity about those BusSpeedTest results you showed... Did you use 80ns or 60ns access time for your motherboard RAM? (=Did you use SpeedRamsey or some other utility to set it to 60ns?)

Hi There!

The motherboard has 70ns RAM, it is EDO FPM. Ramsey was left standard with no tweaks.

Does that help?

Dan

danbeaver wrote: The motherboard has 70ns RAM, it is EDO FPM. Ramsey was left standard with no tweaks.
Does that help?
Dan

Thanks! I got almost the same results _without_ using SpeedRamsey:

op cycle
readw 167.4 ns
readl 313.3 ns
readm 316.9 ns
writew 249.4 ns
writel 482.1 ns
writem 497.5 ns

With SpeedRamsey (I tested a 60ns Simm on my A4000T motherboard) I got:

op cycle
readw 152.6 ns
readl 281.4 ns
readm 280.8 ns
writew 232.8 ns
writel 467.5 ns
writem 465.5 ns

Slightly faster, but still far away from CSPPC memory... So, the only way to get some more 'fast memory' for Classic Amigas seems to to be the UltimatePPC - I really hope it will be finished, and supported by Hyperion !-)

Gregor,

Did you read Calgor's remark about the CSPPC's "PCI" bus meant for the CyberVision card? This has a direct connection to the processor board and possible enough address lines to add a fair chunk of more Fast memory.

Cool beans!

Gregor wrote:Would it be possible to get in the future versions of OS 4.x Classic an option to use ZorRAM boards as part of the Fast memory pool (and not just a SWAP disk)? Is this technically possible?! Yes, I know the memory on ZorRAM is much slower than the memory on CSPPC, but each of us could then decide whether to accept this handicap or not...

We did extensive testing on this with beta testers and developers (we actually did implement it) and it turned out that it slowed down the overall OS too much, so we decided not to go forward with it.

Trust me, the ZorRAM or DKB 3128 is best used only as SWAP in AmigaOS 4.1 Classic.

danbeaver wrote:Gregor,

Did you read Calgor's remark about the CSPPC's "PCI" bus meant for the CyberVision card? This has a direct connection to the processor board and possible enough address lines to add a fair chunk of more Fast memory.

Cool beans!

I'd love to see such a card produced...Are you saying you will make one?

Well I'm more of a chemist than an engineer, but could someone (like J.S.) use an FPGA to implement a serial (yeah PIO) transfer between a USB stack (or is that via a USB stack), memory and a USB device? The alternative is to use a SATA Chipset to implement serial (PIO/DMA) transfers is the same vein?

That bypasses the USB DMA chip issue